欢迎光临依元素科技有限公司!

首页 > 产品展示 > 解决方案
DNReadbacker

DNReadbacker

产品型号 :

2018-07-02 浏览次数: 71
  • 产品介绍
  • 特色
  • 产品规格
  • 实物图片
  • 资源



The debug of FPGA-based designs is a difficult and time intensive task. Several techniques are available to aid in debug. One technique is to route internal FPGA nodes to external I/O pins and then observe those nodes on a logic analyzer or an oscilloscope. Another is to embed a logic analyzer in the FPGA. A problem with either approach is that knowledge of which signals to observe is required prior to place/route. Some tools, Certus™ from Mentor, being an example, have tricks to partially work around this issue. But by and large, if you want observability, you need to know ahead of time what signals you will want to observe.




The DN_Readbacker adds no cost, noninvasive observation to all internal FPGA registers. When invoked, the DN_Readbacker tool reads back the register state of the FPGA(s), maps the resulting data to the netlist, and outputs the result to a .vcd file. The readback can be looped and runs at about 1 cycle/second. The .vcd file can then be analyzed visually using GTKWave or other .vcd file viewer. All FPGAs on the board can be read, along with all FPGAs in a seamless stack.




l Noninvasive real time readback of FPGA register state

Ø 100% coverage FPGA registers

Ø    1 complete readback/second

Ø    Running clock or single step

l    Works on all DINI Group Xilinx-based FPGA boards:

Ø    Xilinx UltraScale, Virtex-7/Kintex-7, Virtex-6

l    Output to standard .vcd file and displayed on GTKWave

l    No RTL support required

Ø    Noninvasive observation of all FPGA registers

Ø    Not necessary to redo synthesis, or place/route


资料下载

联系我们

  • 025-58800523

    电话:025-58800523

  •  sales@e-elements.com

    邮箱:sales@e-elements.com

  • 南京市高新区星火路17号集成电路产业中心B座1003

    地址:南京市高新区星火路17号集成电路产业中心B座1003

×
×