The DNVUF1A is a complete logic prototyping system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The DNVUF1A is a stand-alone system and can be hosted by a 4-lane PCIe cable (GEN3), USB or Ethernet. A single DNVUF1A is configured with a single Virtex UltraScale XCVU440 and can emulate up to 29 million gates of logic as measured by a reasonable ASIC gate counting standard. An infinite number of DNVUF1As can be linked together extending this gate count number 1 billion or more seamlessly. The gate count estimate number does not include embedded memories and multipliers resident in the FPGA fabric. One hundred percent (100%) of the Virtex UltraScale FPGA resources is available to the user application. The DNVUF1A achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Xilinx's 20nm Virtex UltraScale family.
1.Stacking multiple boards together
An infinite number of DNVUF1As can be ganged together to increase the resources. This page here has more detail: Stacking Multiple DNVUFAs boards together. All functionality is seamlessly maintained including the high performance data movement via the TMB (Transceiver Main Bus). Interconnect between FPGAs on a single board and between boards in a stack can be configured on a bank-by-bank basis via cables on the DNBC connectors. Clocks, resets, and configuration are handled seamlessly.
2.Virtex UltraScale FPGA from xilinx
The DNVUF1A uses a high I/O-count, 2892-pin flip-chip BGA package. In this package the VU440 has 1404 I/Os and 48 GTH channels (16 Gb/s). As many I/O.s as possible are utilized. All FPGA to daughter card interconnect is routed as LVDS, but can be used single-ended at a reduced frequency. 100% of the resources of the two Virtex UltraScale FPGAs is dedicated to the user application.
Introducing the Xilinx Virtex UltraScale VU440. This is the only device that can be stuff on this product. The XCVU440 is available in three speed grade (fastest to slowest): -3, -2, -1. We estimate that the VU440 can prototype >29 million gates of ASIC logic with plenty of resource margin. This is a ground breaking device and the second generation family from Xilinx to utilize 2.5 silicon dimensions. Prior to the stacked-silicon VU440, the biggest challenge in FPGA-based ASIC prototyping was logic partitioning. This difficult task is nearly eliminated with this large 3-slice device.
3.The Marvell MV78200 Discovery™ Dual CPU
A MONSTER for data movement and manipulation
Easy FPGA configuration is a required feature of large FPGA boards. We use a custom socketed CPU card to handle this function. We choose a Marvell MV78200 from the DiscoveryTM Innovation CPU family. Bluntly stated, this CPU is massive, massive overkill for the mundane task of FPGA configuration. The MV78200 comes a variety high performance interfaces, and all can be utilized to your advantage. Look forward to a higher performance CPU card in the near future.
4.Dual Sheeva CPUs, 1GHz with floating point
First and foremost are dual CPUs. And after we are done configuring the FPGAs we dedicate both CPUs to your application. The CPUs in the MV78200 are Marvell Sheeva. cores, which are ARM v5TE compliant. The CPUs are clocked at 1GHz and each processor has a single and double precision floating point unit. A fixed 1 GB, DDR2 memory is standard and is useful for large amounts of high speed data buffering. The memory is organized as 128M x 64 and clocked at the full frequency allowed: 400MHz (800MHz effective with DDR). This DDR2 bank is shared between the two CPUs. Boot code is resident in an SPI Flash, and application code is downloaded via any port: PCIe, USB, and Ethernet. We ship Linux as the standard operating system. Options exist forVxWorks and other real-time operating systems. Contact the factory for more information.
The Marvell 78200 acts as a two-port high-speed PCI Express switch (2.5 Gb/s). It connects the user FPGA at 4-lane PCI Express speeds to a host computer. The Marvell 78200 has multiple DMA engines to pump data to and from any port. The user interface on the FPGA is a simple-to-use, pipelined A/D bus running at 6.4Gb/s. Drivers for data movement to and from a host machine are provided. A simple example FPGA design and host computer application streaming data at PCI Express x4 bandwidth to the user FPGA is provided.
6.Two Serial-ATA Ports (SATA II)
The MV78200 has two Serial-ATA Generation 2 (SATA II) ports, each capable of running at 3.0 Gb/s. SATA is intended for high speed data transfer to/from serial-ATA hard drives. Two SATA connectors are provided, allowing for direct, high-speed interfacing to external hard drives. The MV78200 has specialized enhanced DMA (EDMA) engines for HDD data transfer with 512-byte buffer for each channel. Examples of all possible data movement options, with source, are included.
7.GbE - 802.3 Gigabit Ethernet
The MV78200 can be controlled over its built-in Ethernet port. The interface is a standard RJ45 connector. This port can be used to configure FPGAs, set board clocks and other resources, and access the Linux terminal. This terminal can also be used to send data to and from the user FPGA design at gigabit Ethernet speeds.
8.Bank-Granular Expansion connectors for customization, memory, and stacking
The DNVUF1A uses a connector standard called DNBC (DINI Bank Connector), which utilizes a Samtec SEAM series connectors. Twenty four of these connectors are attached to the FPGA, enabling expansion, customization, and stacking. This is a non-proprietary, industry standard connector from Samtec and the mating connector is readily available. We can provide the mating connector to you at our cost. We are not fans of proprietary, hard-to-get, outrageously priced expansion connectors. Of the 52 signals in the bank, 24 pairs are routed differentially and can run at the limit of the Virtex UltraScale FPGA I/Os: TBD MHz. The remaining 4 signals are routed single-ended. Clocks, resets, and cable/daughter card presence detection, along with abundant (fused) power are included in each connector.
Memory can be added to the DNVUF1A via the DNBC expansion connector using theDNBC3_SODM204 expansion card. Three DNBC connectors can host a singleDNBC3 expansion card. Eight of these cards can be used on a single DNVUF1A. The DNBC3_SODM204 has a 204-pin SODIMM socket. Off-the-shelf DDR3 SODIMM modules work fine, allowing you to add up to 8GB of low cost memory in each position. In addition, we have compatible SODIMMs in the following variations: flash, SSRAM, QDR II+, mobile SDRAM, mictors, USB2.0 PHYs, and more. DDR4 is available on DNBC3_DDR4.
10.Easy Configuration via PCIe, USB, or Ethernet
Configuration of the FPGAs is under the control of the Marvell CPU. Configuration data can be provided over PCI Express, USB, Ethernet, or on-board non-volatile memory. The configuration files can be copied to the board using a USB memory stick (provided). Configuration occurs automatically after the CPU boots. Sanity checks are performed automatically on the configuration files, streamlining the configuration process in the case of human error. Multiple LEDs provide instant status and operational feedback.
11.Status LEDs, Debug
As with all of our ASIC emulation boards, the DNVUF1A is loaded with LEDs. The LEDs are stuffed in several different colors (red, green, blue, orange et al.). There are enough LEDs here to attract ants. Please don.t do this without adult supervision. These LEDs are user controllable from the FPGAs so can be used as visual feedback in addition to collecting insects. A JTAG connector provides an interface to Vivado Integrated Logic Analyzer (ILA) and other third party debug tools. A DNBC daughter card enables a ProtoLinkTM interface.
l Four Xilinx Virtex UltraScale FPGAs (A2892):
Ø VU440-3, -2, -1 (fastest to slowest)
Ø 29+ million ASIC gates (ASIC measure)
l Hosted via
Ø 8-lane GEN3 PCIe via iPASS cable
Ø 10/100/1000BASE-T Ethernet
Ø USB 2.0
l DDR4 Memory can be added using DINAR2_SODM204 using 3 DINAR2 expansion connectors
Ø DNSODM204_QUADMIC (four Mictor connectors)
Ø DNSODM204_SE (mobile SDRAM)
Ø DNSODM204_USB (USB2.0 PHY)
Ø DNSODM204_MICTOR_IO (dual Mictor connectors)
l High Speed interfaces:
Ø 2 - QSFP+ module for 4x 10 GbE or single 40 GbE
Ø 8 - SFP+ modules for 10 GbE
l DNTC (DINI Transceiver Connector), 16-lanes each. One per FPGA. Each capable of supporting:
Ø 16-lane PCIe (GEN1/GEN2/GEN3)
Ø 2x CX4-Ethernet, XAUI, Infiniband
Ø 16x SFP+ modules for 10 GbE
Ø 4x QSFP+ modules for 40 GbE
Ø 16x USB3.0/2.0 (A,AB,B)
Ø 16x Serial ATA II (SATA II)
Ø 16x SMA
l TMB busses - Preconfigured high speed data movement between field FPGAs and Config FPGA
Ø 5 GB/s DMA between FPGAs and Config FPGA
l Main Bus (YMB) for bussed interconnect between all four FPGAs
Ø 40 signals, single-ended
l Marvel MV78200 Discovery Innovation Dual CPU
Ø 1 GHz clock
Ø Dual USB2.0 ports (Type B connector)
Ø Dual Serial-ATA II connectors for 2 external hard drives (SATA II)
Ø Gigabit Ethernet interface
l 10/100/1000 GbE (RJ45 connector)
Ø Sheeva™ CPU Core (ARM v5TE compliant)
l Out-of-order execution
l Single and double-precision IEEE compliant floating point
l 16-bit Thumb instruction set increases code density
l DSP instructions boosts performance for signal processing applications
l MMU to support virtual memory features
l Dual Cache: 32 KB for data and instruction, parity protected
l L2 cache: 512 KB unified L2 cache per CPU (total of 1MB), ECC protected.
Ø 1 GB external DDR2 SDRAM
l Organized in a 128M x 64 configuration
l 400 MHz (800 MHz data rate with DDR)
Ø RS232 port for terminal-style observation
Ø After configuration, both CPUs dedicated entirely to user application
Ø Linux operating system
l Source and examples provided via GPL license (no charge)
l ~15 seconds to CPU boot
l Five independent low-skew global clock networks and single fixed clock
Ø Five, high-resolution, user-programmable synthesizers for G0-G4
l Silicon Labs Si5326: 2kHz to 945 MHz
Ø User configurable via Marvell uP RS232, USB, PCIe, or Ethernet
Ø Global clocks networks distributed differentially and balanced
l Flexible customization and stacking via 18 daughter card connectors per FPGA
Ø DNBC (DINI Bank Connector) expansion connector
l One bank per connector
l Daughters cards (1 to 12 connectors
l Added FPGA to FPGA interconnect for stacking
l Connector: non-proprietary; readily available; cheap
l 24 LVDS pairs + 4 single-ended, + clocks
Ø TBD(800MHz?) on all signals with source synchronous LVDS
Ø Signal voltage set by daughter card (+1.0V to +1.8V)
Ø Supplied power rails (fused):
l +12V (24W max), +3.3V (10W max)
Ø Pin multiplexing to/from daughter cards using LVDS (up to 10x)
l Noninvasive debug via FPGA register readback: DN_Readbacker
l Fast and Painless FPGA configuration
Ø USB, cabled PCIe, Ethernet, JTAG
Ø Stand-alone configuration with USB stick
Ø Configuration Error reporting
Ø Accelerated configuration readback for advanced debug
l RS232 port for embedded FPGA-based SOC uP debug
Ø Accessible from all FPGAs via separate 2-signal bus
l Full support for embedded logic analyzers via JTAG interface
Ø Vivado Logic Analyzer and other third party solutions.
l Status FPGA-controlled LEDs:
Ø Enough multicolored LEDs to attract ants..